| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock signal reproduction PLL circuit which operates with high stability and is capable of reproducing a clock signal with high accuracy in the clock signal reproduction PLL circuit for reproducing the clock signal from a signal read and generated from a recording medium. <P>SOLUTION: A correction means is arranged for correcting a clock signal outputted based on the reproduced clock signal. Especially, the correction means is constituted of a clock signal measurement means for measuring the frequency of the outputted clock signal, a comparison and discrimination means for performing comparison and discrimination between a measurement result by this clock signal measurement means and a predetermined management range, and an output control means for outputting a preset clock signal as a clock signal based on the result of the discrimination by this comparison and discrimination means. Further, the correction means is provided with an adjustment control signal generation means for outputting an adjustment control signal for adjusting an offset and/or a gain in the clock signal reproduction PLL circuit, and an adjustment means for making an adjustment according to this adjustment control signal. <P>COPYRIGHT: (C)2004,JPO |
