| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory circuit in which erroneous read-out caused by level floating of the source line caused by a discharge current flowing into the source line from a pre-charged bit lines is prevented at the time of read-out, erroneous read-out based on capacity coupling between adjacent bit lines also is not caused, and large scale high integration can be performed. <P>SOLUTION: At the time of setting a read-out mode, erroneous red-out caused by level floating of a source line caused by that pre-charge electric charges on the bit line flows in the source line at the time of discharge is prevented by connecting almost all the bit lines other than bit lines connected to a selected read-out memory cell to a VSS level, also, erroneous read-out caused by variation of a potential of the selected bit line caused by capacity coupling between adjacent bit lines can be prevented. <P>COPYRIGHT: (C)2004,JPO |
