发明名称 PATH DELAY MEASURING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To automatically measure the path delay of a combination circuit without any LSI tester in a path delay measuring circuit which compares, with an expected value, an output of the combination circuit fetched in by a capture action using the mechanism of a scan test circuit, and varies the time required for performing the capture action, thereby determining signal transition time of the combination circuit. SOLUTION: The path delay measuring circuit comprises a pattern generating circuit 10 which generates a test pattern to be given to a combination circuit 101; a comparing/determining circuit 106 which compares an output of the combination circuit with an expected value; a clock generating circuit 301 with a clock mode counter outputting a clock mode value updated in each determination of signal transition time, which generates a clock in which the clock interval of the time required for performing a capture action depending on the clock mode value can be varied; and a timing signal generating circuit 107 which supplies action timing signals of the respective circuits. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004157090(A) 申请公布日期 2004.06.03
申请号 JP20020325359 申请日期 2002.11.08
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KOBAYASHI TAKUYA
分类号 G01R31/28;G01R31/3183;H01L21/66;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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