发明名称 PROCESSOR CACHE MEMORY AS RAM FOR EXECUTION OF BOOT CODE
摘要 In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the exe­cuting boot code stream as a memory store.
申请公布号 WO2004046920(A2) 申请公布日期 2004.06.03
申请号 WO2003US34808 申请日期 2003.10.30
申请人 INTEL CORPORATION 发明人 DATTA, SHAM;ZIMMER, VINCENT;VAID, KUSHAGRA;STEVENS, WILLIAM;SANTONI, AMY
分类号 G06F9/445;G06F12/08;G06F12/12 主分类号 G06F9/445
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