| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory macro and a semiconductor integrated circuit which can reduce the surface area occupied by wiring of an upper layer, without impairing versatility. <P>SOLUTION: The memory macro is provided with a memory array 13, a connection circuit 15 as an interface with the memory array 13, and a signal wiring section 14 for connecting the memory array 13 and the connection circuit 15. Meshed wiring lines 21, 22 of first and second wiring layers are provided on the memory array 13. The connection circuit 15 is connected to a plurality of signal lines 17 as a third wiring layer provided on the memory array 13, the connection circuit 15 or the signal wiring section 14 by means of intermediate wiring lines. A zone, provided with intermediate wiring lines 18, is arranged on the memory array 13 or on the signal wiring section 14, and the meshed wiring lines 22 as the second wiring layer do not present in the zone provided with intermediate wiring lines 18. <P>COPYRIGHT: (C)2004,JPO |
