| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an EEPROM which allows random access to be accelerated, as a result of the reduction in the floating of a source line by forming the source line into low resistance without increasing the chip area. <P>SOLUTION: This memory comprises a memory cell section constituted by one cell or a plurality of non-volatile memory cells, a signal line to perform data transfer with the memory cell section, and a selective transistor located between the signal line and the memory cell section. In write-protected operation, writing non-selective voltage is applied to the signal line, and by applying selective gate voltage higher than the writing non-selective voltage to a gate of the selective transistor, the writing non-selective voltage is transferred to a channel of the memory cell section. Writing gate voltage is then applied to a control gate of the memory cell, and write-protected channel voltage boosted by capacity coupling between the channel and the control gate of the memory cell is generated. <P>COPYRIGHT: (C)2004,JPO</p> |
