发明名称 FERROELECTRIC MEMORY ARRAY
摘要 <p>A ferroelectric memory array capable of reliably and nondestructively reading out a stored logical value from only a selected memory cell without being affected by other memory cells. When connecting a drain (13) of each ferroelectric gate field effect transistor Fij to drain wiring, the drain (13) is connected via drain wiring Dk to a drain (13) of one or more ferroelectric gate electric field effect transistors selected from ferroelectric gate electric field effect transistors other than the ferroelectric gate electric field effect transistor having a source (12) connected to a source wiring Bj which is connected to the local source (12) and other than the ferroelectric gate electric field effect transistor having a gate electrode (15) connected to a gate wiring Ai which is connected to the local gate electrode (15).</p>
申请公布号 WO2004047176(A1) 申请公布日期 2004.06.03
申请号 WO2003JP14704 申请日期 2003.11.19
申请人 NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE;SAKAI, SHIGEKI 发明人 SAKAI, SHIGEKI
分类号 G11C11/22;H01L21/28;H01L21/336;H01L21/8246;H01L21/8247;H01L27/105;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L27/105 主分类号 G11C11/22
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