发明名称 Measurement architecture to obtain per-hop one-way packet loss and delay in multi-class service networks
摘要 An architecture for measurement of per-hop, one-way delay includes a input observation circuit (24) at the input interface of a node (12) and a output observation circuit (26) at the output interface (16) of a node (12). The input observation circuit (24) copies and time stamps the headers of incoming packets, and filters packets according to an aggregate definition. Similarly, the output observation circuit (26) copies and time stamps the headers of outgoing packets, and filters packets according to the aggregate definition. The incoming and outgoing traces are correlated to calculate a delay measurement. A packet loss measurement uses input observation circuits (72a and 72b) at the input interfaces (14) of upstream and downstream nodes (20 and 22) and an output observation circuit 74 at the output interface (16) of the upstream node. The observation circuits (72a, 72b and 74) determine the number of lost packets across a node and between nodes, according to an aggregate definition.
申请公布号 US2004105391(A1) 申请公布日期 2004.06.03
申请号 US20020307133 申请日期 2002.11.29
申请人 CHARCRANOON SARAVUT 发明人 CHARCRANOON SARAVUT
分类号 H04L12/56;H04L12/26;(IPC1-7):H04L12/56 主分类号 H04L12/56
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