发明名称 NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages
摘要 A nonvolatile semiconductor memory device includes a NAND memory cell array, booster circuit, row decoder, bit line control circuit and column decoder. In the device, the magnitude of intermediate voltage applied to the control gates of memory transistors from the booster circuit via the row decoder is changed according to the position of a selected control gate line when data is sequentially programmed into the memory transistors in the memory cell array. Alternatively, a plurality of different intermediate voltages are applied when data is simultaneously programmed into memory transistors connected to the selected control gate line.
申请公布号 US2004105308(A1) 申请公布日期 2004.06.03
申请号 US20030405233 申请日期 2003.04.03
申请人 MATSUNAGA YASUHIKO;YAEGASHI TOSHITAKE;ARAI FUMITAKA 发明人 MATSUNAGA YASUHIKO;YAEGASHI TOSHITAKE;ARAI FUMITAKA
分类号 G11C16/06;G11C16/02;G11C16/04;G11C16/10;H01L27/115;(IPC1-7):G11C16/04;G11C11/34 主分类号 G11C16/06
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