发明名称 |
2T2C SIGNAL MARGIN TEST MODE USING A DEFINED CHARGE EXCHANGE BETWEEN BL AND/BL |
摘要 |
<p>The present invention provides at test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.</p> |
申请公布号 |
WO2004047115(A1) |
申请公布日期 |
2004.06.03 |
申请号 |
WO2003SG00262 |
申请日期 |
2003.11.11 |
申请人 |
INFINEON TECHNOLOGIES AG;JOACHIM, HANS-OLIVER;JACOB, MICHAEL;REHM, NORBERT |
发明人 |
JOACHIM, HANS-OLIVER;JACOB, MICHAEL |
分类号 |
G11C29/50;(IPC1-7):G11C29/00;G11C11/22 |
主分类号 |
G11C29/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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