| 摘要 |
PROBLEM TO BE SOLVED: To facilitate the enhancement of semiconductor device integration density and ultraminiaturization. SOLUTION: A p-well region 2 and an n-well region 3 are layered on the upper surface of a silicon wafer 1, a 0.05-0.1μm-deep trench 4 is formed near the boundary between the p-well region 2 and the n-well region 3, and a gate oxide film 5 is formed to cover the entire surface of the silicon wafer 1. n<SP>+</SP>-diffused layers 8a and 8b are formed on the p-well region 2 in the bottom of the trench 4 and on the surface of the silicon wafer 1 in contact with the upper end of a trench side wall 4a, and p<SP>+</SP>-diffused layers 11a and 11b are formed on the n-well region 3 in the bottom of the trench 4 and on the surface of the silicon wafer 1 in contact with the upper end of a trench side wall 4b. Gate electrodes 12a and 12b are formed on the side walls 4a and 4b of the trench 4 with the gate oxide film 5 in between, a silicon oxide film 13 is formed to cover the gate electrodes 12a and 12b, and, electrodes 14a, 14b, and 14c are formed in contact with diffused layers 8 and 11 through the silicon oxide film 13. COPYRIGHT: (C)2004,JPO
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