发明名称 |
Static pass transistor logic with transistors with multiple vertical gates |
摘要 |
Systems and methods are provided for static pass transistor logic having transistors with multiple vertical gates. The multiple vertical gates are edge defined such that only a single transistor is required for multiple logic inputs. Thus a minimal surface area is required for each logic input. The novel static pass transistor of the present invention includes a transistor which has a horizontal depletion mode channel region between a single source and drain region. A number of vertical gates are located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. At least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. According to the present invention, there is no source nor drain region associated with each input and the gates have sub-lithographic horizontal dimensions by virtue of being edge defined vertical gates. |
申请公布号 |
US6744082(B1) |
申请公布日期 |
2004.06.01 |
申请号 |
US20000580901 |
申请日期 |
2000.05.30 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
FORBES LEONARD;AHN KIE Y. |
分类号 |
H01L21/28;H01L21/336;H01L21/8239;H01L29/423;H01L29/78;H01L29/788;(IPC1-7):H01L29/792 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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