| 摘要 |
PURPOSE: A scan chain type integrated circuit and a test method thereof are provided to reduce vector size and test time by supplying a serial scan vector to a register connected to an output cell directly, without going through logic gates of the integrated circuit. CONSTITUTION: A plurality of input cells(10) input external parallel data in a normal mode. A plurality of output cells(70) output internal parallel data in the normal mode, and output a scan vector in a test mode. A scan vector input cell(20) inputs the scan vector in the test mode. A scan vector output cell(60) outputs the scan vector in the test mode. The first and the second logic unit(40,50) are connected in parallel between the plurality of input cells and output cells to process the internal parallel data. And a plurality of registers(30) are connected between the input cells and the output cells to transmit the external parallel data to the first logic unit and to supply the internal parallel data to the output cell in the normal mode, and are shifted in sequence in response to a clock signal in the test mode, and are connected serially to supply the shifted scan vector to the output cell.
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