发明名称 Graphics display system with video synchronization feature
摘要 A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples. The time base corrector receives samples at the output of the line-locked sample rate converter and provides samples synchronized to the display clock for reducing undesirable artifacts such as jitter.
申请公布号 US6744472(B1) 申请公布日期 2004.06.01
申请号 US19990437207 申请日期 1999.11.09
申请人 BROADCOM CORPORATION 发明人 MACINNIS ALEXANDER G.;TANG CHENGFUH JEFFREY;XIE XIAODONG;PATTERSON JAMES T.;KRANAWETTER GREG A.
分类号 G06T9/00;G09G1/16;G09G5/00;G09G5/02;G09G5/06;G09G5/12;G09G5/14;G09G5/28;G09G5/34;G09G5/36;G09G5/39;G09G5/395;G09G5/42;H04N5/12;H04N5/14;H04N5/44;H04N5/445;H04N5/45;H04N5/46;H04N7/01;H04N7/26;H04N7/50;H04N9/45;H04N9/64;H04N11/14;H04N11/20;(IPC1-7):H04N7/01;H04N9/66;H03M7/00 主分类号 G06T9/00
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