发明名称 |
Block move engine with macroblock addressing modes |
摘要 |
An apparatus comprising a first circuit and a second circuit. The first circuit may be conf igured to generate an address signal in response to (i) a first ramp signal, (ii) a second ramp signal, and (iii) a format signal. The second circuit may be configured to generate the first and second ramp signals in response to a one or more control signals. The address signal may support a raster format when the format signal is in a first state and may support a macroblock format when the format signal is in a second state.
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申请公布号 |
US6744428(B1) |
申请公布日期 |
2004.06.01 |
申请号 |
US20010878594 |
申请日期 |
2001.06.11 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
PETHER DAVID N.;RATCLIFFE MARTIN J. |
分类号 |
G09G5/00;G09G5/397;(IPC1-7):G09G5/00 |
主分类号 |
G09G5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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