| 摘要 |
Memory modules and a controller are arranged and two clock lines are provided to go and return along the arrangement of the memory modules and the controller. A first basic clock and a second basic clock having twice the cycle period of the first basic clock are transferred over the go portions of the respective clock lines to the memory modules and the controller. After passing through the turnaround point, the first and second basic clocks are transferred as return clocks over the return portions of the clock lines to the memory modules and the controller. The first and second basic go clocks and the first and second basic return clocks are fed into the memory modules and the controller. The input/output operation of data is controlled synchronously with these clocks.
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