METHOD FOR FABRICATING POWER IC USING SOI SUBSTRATE

摘要

PURPOSE: A method for fabricating a power IC using an SOI substrate is provided to enhance resolution of a display unit by improving and optimizing the accuracy of a fabrication process. CONSTITUTION: A first trench(34a) and a second trench(34b) are formed by etching partially an SOI substrate(31). A well of an LDMOS element, a floating region, and a well of a CMOS element are formed within the SOI substrate. The first and the second field oxide layer(42a,42b) are buried into the first and the second trenches. A third field oxide layer(42c) is formed on the floating region. A thick gate insulating layer(45a) of the LDMOS element and a thin gate insulating layer(45b) of the CMOS element are formed thereon. A gate electrode(46a) of the LDMOS element and gate electrodes(46b,46c) of the CMOS element are formed simultaneously. An LDD region of the LDMOS element and an LDD region of the CMOS element are formed within the SOI substrate of both sides of the gate electrodes. Spacers are formed on sidewalls of the gate electrodes, respectively. A source region of the LDMOS element and a source/drain region of the CMOS element are formed, respectively.