| 摘要 |
The voltage-limiting circuit (16) comprises at least one p-n junction (DPN) having a breakdown voltage (Vppmax) defining a trigger threshold of the circuit on the basis of which the p-n junction is conducting by the avalanche effect. The circuit also comprises a load (LD) in series with the p-n junction for limiting the avalanche current (I1), and at least one switch (SW) in parallel with the p-n junction and the load. The switch (SW) is open when the junction is nonconducting and closed when the junction is conducting. The load (LD) is chosen so that the avalanche current (I1) passing through the p-n junction is at least two times below the current (I2) passing through the switch (SW) when the circuit is triggered. The p-n junction is a junction of an n-MOS transistor connected as a diode, and the load (LD) comprises a p-MOS transistor. The switch (SW) comprises a p-MOS transistor which is connected as a current0mirror with the p-MOS transistor of the load (LD). An integrated circuit (claimed) comprises the voltage-limiting circuit (claimed) connected at the output of a voltage generator delivering a voltage (Vpp), and the voltage generator is an overvoltage circuit. A voltage regulator (claimed) comprises the voltage-limiting circuit and means for delivering a logic signal (on/off) when the circuit is triggered. A method (claimed) for limiting a voltage (Vpp) by use of a p-n junction is implemented by the circuit and consists in limiting the avalance current by a load, and closing a switch in parallel when the junction is conducting.
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