| 摘要 |
An input data processing circuit according to one aspect of the present invention comprises a phase detector 50 adapted to detect a clock phase difference between the first and second clocks which are sent from doubled circuits. The readout circuitry 60 selects one of the first and second FIFO buffers (10 or 30) if the clock phase difference is greater than a predetermined time corresponding to a half of data length of the frame, namely, "m" bytes of the input data sets. In this case, the selected FIFO buffer (10 or 30) has a faster clock by the clock phase difference than another clock between the first and second clocks. Then the readout circuitry 60 reads the frame out of only the selected FIFO buffer. As the results, no occurrence of "data lack" in FIFO buffers even if a clock rate difference exists between clocks generated by doubled circuits.
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