发明名称 Semiconductor circuit device capable of high speed decoding
摘要 An address signal is transferred from an address bus transmitting an address from an address generation circuit, to a real address bus connecting to a decoder for decoding an applied address signal, via a branch node, a branch address bus and contacts. The real address bus and the branch address bus are electrically connected at a plurality of points using the contacts. The branch address bus functions as a lining or backing signal line to the real address bus, and a line resistance and line capacitance of the real address bus can be equivalently reduced. A variation in signal propagation delay over an entire decoding circuits is suppressed.
申请公布号 US2004100305(A1) 申请公布日期 2004.05.27
申请号 US20030442132 申请日期 2003.05.21
申请人 RENESAS TECHNOLOGY CORP. 发明人 KOKUBO NOBUYUKI;HOSOGANE AKIRA;TOMITA HIDEMOTO
分类号 G11C11/41;G11C11/401;G11C11/413;H01L27/02;H03K19/00;(IPC1-7):H03K19/00 主分类号 G11C11/41
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