发明名称 |
TRAFFIC MANAGEMENT ARCHITECTURE |
摘要 |
An architecture for sorting incoming data packets in real time, on the fly, processes the packets and places them into an exit order queue before storing the packets. This is in contrast to the traditional way of storing first then sorting later and provides rapid processing capability. A processor (22) generates packet records from an input stream (20) and determines an exit order number for the related packet. The records are stored in an orderlist manager (24) whilst the data portions are stored in memory hub (21) for later retrieval in the exit order stored in the manager (24). The processor (22) is preferably a parallel processor array using SIMD and provided with rapid access to shared state (23) by a state engine. |
申请公布号 |
WO2004045162(A2) |
申请公布日期 |
2004.05.27 |
申请号 |
WO2003GB04893 |
申请日期 |
2003.11.11 |
申请人 |
CLEARSPEED TECHNOLOGY LIMITED;SPENCER, ANTHONY |
发明人 |
SPENCER, ANTHONY |
分类号 |
H04L12/54;H04L12/823;H04L12/851;H04L12/861;H04L12/863;H04L12/869;H04L12/875 |
主分类号 |
H04L12/54 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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