| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory controller that increases area use efficiency by accommodating devices of a plurality of bus widths while suppressing increase in the number of terminals. SOLUTION: A computer system comprises a CPU for managing a memory with a plurality of areas of different bus widths and outputting area selection signals each for selecting any area in the memory and an address signal, an area selection OR circuit 22 for computing the logical sum of the plurality of area selection signals from the CPU, and an area control circuit 23 for dividing the area of the CPU in dependence on the address signal 21 from the CPU and the area selection signal from the area selection OR circuit 23 and generating a plurality of device selection signals. Even when devices of a plurality of bus widths are connected, an area of the CPU corresponding to each bus width can provide access, so that the devices of a plurality of bus widths can be accommodated under suppressed increase in the number of terminals. COPYRIGHT: (C)2004,JPO
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