REGISTER CONTROLLED DELAY LOCKED LOOP HAVING ACCELERATION MODE

摘要

PROBLEM TO BE SOLVED: To provide a register controlled delay locked loop which improves the deterioration of precision caused by accelerating an operating speed of an element.

SOLUTION: The register controlled delay locked loop is provided with: delay lines 54, 55 each having a plurality of unit delay cells for delaying an internal clock; a delay model 59 for reflecting the internal clock passed through the delay line with delay conditions of a real clock passage; a delay means 63 for delaying an output signal of the delay model for fixed time; a first phase comparator 60 for comparing a phase of the output signal of the delay model with a phase of the internal clock; a second phase comparator 64 for comparing a phase of the output signal of the delay means with the phase of the internal clock; a mode determination part 65 for determining whether an acceleration mode is to be advanced or to be stopped in response to output signals of the first and second phase comparators; a shift register controller 61 and a shift register 62 for controlling delay quantities of the delay lines in response to output signals of the first phase comparator and the mode determination part.

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