| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a data demodulation circuit decreased in a chip size by simplifying a circuit configuration and reducing a circuit mount area. <P>SOLUTION: This invention is provided with the following units. A 1st PLL circuit: a wobble signal and a 1st reference clock signal are clocked in frequency and phase. A frequency/phase comparator (FPC): a 1st output signal from the 1st PLL circuit is compared with a system clock signal, and a 2nd output signal is outputted based on the difference between the frequencies and phases.A PLL filter: a 3rd output signal is outputted by setting a predetermined cut-off for the 2nd output signal. A pulse width modulation circuit: a pulse wave having a 2nd reference clock signal as the carrier frequency is generated, and a 4th output signal is generated wherein the wave is pulse-width-modulated by the 3rd output signal. A low-pass filter: the 4th output signal is smoothed to output a 5th output signal. A VCO circuit: the 5th output signal is used as a control voltage. A 1st frequency divider circuit: an output signal of the VCO circuit is frequency divided by N to be output as a system clock signal. A 2nd frequency divider circuit: the system clock signal is frequency divided by M to be fed back to the frequency/phase comparator. <P>COPYRIGHT: (C)2004,JPO |
