发明名称 |
Use of silicon block process step to camouflage a false transistor |
摘要 |
A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.
|
申请公布号 |
US2004099912(A1) |
申请公布日期 |
2004.05.27 |
申请号 |
US20030637848 |
申请日期 |
2003.08.07 |
申请人 |
HRL LABORATORIES, LLC. |
发明人 |
CHOW LAP-WAI;CLARK WILLIAM M.;HARBISON GAVIN J.;BAUKUS JAMES P. |
分类号 |
H01L23/58;H01L27/02;(IPC1-7):H01L29/76 |
主分类号 |
H01L23/58 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|