Integrated memory circuit permits read and write operations during single clock cycle, using data transfer controller

摘要

The circuit includes memory blocks (MB1-MB4) comprising sub memory blocks (SMB1-SMBM). One register (CMB1-CMB4) is associated with each memory block (MB1-MB4). A data transfer controller (210) reacts to read- and write addresses, by reading or writing data as appropriate, from or to the memory blocks and registers. The controller reads from or writes to a memory block, and simultaneously writes data to or reads from a register, when higher order digits of the read and write addresses are identical. An Independent claim is included for the corresponding method.