| 摘要 |
PROBLEM TO BE SOLVED: To provide a synchronous memory device capable of shortening a test time. SOLUTION: This device is provided with a bank having first and second unit blocks 110. 150 including a plurality of cell arrays, and first and second decoding means decoding inputted column addresses YA<0>∼YA<9> and outputting respectively column selecting signals of the second unit blocks. Also, the device has a column address transmitting means enabling simultaneously both decoding means independently of the two unit block selecting bit signals out of column addresses at the time of a test mode, a combination circuit for first test combining data for test outputted by the column selecting signal of each unit block at the time of a test mode and detecting whether data for test previously stored is erroneous or not, and a combination circuit for second test, and the device is provided with first and second output pads 510, 520 outputting respectively and independently output of the combination circuit 600 for the first test and output of the combination circuit 600' for the second test. COPYRIGHT: (C)2004,JPO
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