PIPELINES OF MULTITHREADED PROCESSOR CORES FOR PACKET PROCESSING
摘要
A method of parallel hardware-based multithreaded processing is described. The method includes assigning tasks for packet processing to programming engines and establishing pipelines between programming stages, which correspond to the programming engines. The method also includes establishing contexts for the assigned tasks on the programming engines and using a software controlled cache such as a CAM to transfer data between next neighbor registers residing in the programming engines.
申请公布号
WO03065207(A3)
申请公布日期
2004.05.27
申请号
WO2003US01580
申请日期
2003.01.16
申请人
INTEL CORPORATION (A DELAWARE CORPORATION)
发明人
ADILETTA, MATTHEW;BERNSTEIN, DEBRA;WILKINSON, HUGH;WOLRICH, GILBERT;ROSENBLUTH, MARK