发明名称 Electronic apparatus test circuit
摘要 The invention provides an electronic apparatus test circuit that can reduce the testing time and cost without relying on a PLL circuit. An electronic apparatus test circuit in accordance with the present invention is equipped with a PLL circuit, an external clock circuit that outputs either a multiplied clock signal or an external clock signal according to the state of a test signal, a divider circuit that divides the multiplied clock signal or an external clock signal to generate and output a system clock signal for a logic circuit and a clock signal for an encoder circuit, an input cell, a reception circuit, a decoder circuit, a logic circuit that processes with a specified logic circuit decoded data according to a system clock signal for the logic circuit, an encoder circuit that encodes the processed data according to a clock signal for the encoder circuit, a transmission circuit that transmits the encoded data, and an output cell.
申请公布号 US6741094(B2) 申请公布日期 2004.05.25
申请号 US20020273170 申请日期 2002.10.18
申请人 SEIKO EPSON CORPORATION 发明人 OGAWA TAKAO
分类号 G01R31/28;G01R31/317;G01R31/3183;G06F3/00;G06F7/38;H03K19/00;(IPC1-7):H03K19/00 主分类号 G01R31/28
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