发明名称
摘要 A NAND flash memory device includes a first and second memory blocks. A shared row selection circuit is provided between the first and second memory blocks, selectively or simultaneously selecting the first and second memory blocks, and transferring wordline voltages to a selected memory block by means in a multi-boosting manner.
申请公布号 KR100432884(B1) 申请公布日期 2004.05.22
申请号 KR20010082417 申请日期 2001.12.21
申请人 发明人
分类号 G11C16/06;G11C16/04;G11C16/08 主分类号 G11C16/06
代理机构 代理人
主权项
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