发明名称 |
PLL USING UNBALANCED QUADRICORRELATOR |
摘要 |
<p>A Phase Locked Loop (1) used in a data and clock recovery comprising a frequency detector (10) including a quadricorrelator (2), the quadricorrelator (2) comprising a frequency detector including double edge clocked bi-stable circuits (21, 22, 23, 24) coupled to a first multiplexer (31) and to a second multiplexer (32) being controlled by a signal having a same bitrate as the incoming signal (D), and a phase detector (DFF) controlled by a first signal pair (PQ, PQ) provided by the first multiplexer (31) and by a second signal pair (PI, PI) provided by the second multiplexer (32).</p> |
申请公布号 |
WO2004042927(A1) |
申请公布日期 |
2004.05.21 |
申请号 |
WO2003IB04462 |
申请日期 |
2003.10.08 |
申请人 |
SANDULEANU, MIHAI, A., T.;KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
SANDULEANU, MIHAI, A., T. |
分类号 |
H04L7/027;H03D13/00;H03L7/087;H03L7/091;(IPC1-7):H03L7/091 |
主分类号 |
H04L7/027 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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