DEBUGGING USING CONTROL-DATAFLOW GRAPH WITH RECONFIGURABLE HARDWARE EMULATION

摘要

An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm whi ch utilizes a runtime selectable emulation library that emulates a reconfigurab le processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm. Another embodiment of the invention includes a method of simulating a control-dataflow graph that includes building an internal representation of the control-dataflow graph that includes one or more dataflow code blocks, and simulating the control- dataflow graph as a sequence of code block dataflow executions, where contro l is passed from one code block to another code block based on the output valu e of the code block until EXIT is reached.