发明名称 |
SEMICONDUCTOR MEMORY DEVICE HAVING CONFIGURATION OF SELECTING DESIRED DLL CLOCK, IN WHICH DESIRED DLL CLOCK IS SELECTED ACCURATELY |
摘要 |
PURPOSE: A semiconductor memory device having a configuration of selecting a desired DLL clock is provided to select a DLL(Delay Locked Loop) clock corresponding to a desired external clock accurately, even though a cycle time is short. CONSTITUTION: The semiconductor memory device(510) comprises a clock port(512) and a control signal port(514) and an address port(516) and a data input/output port(518) and a data strobe signal input/output port(520). The clock port receives external clock signals(EXTCLK,EXTZCLK) and a clock enable signal(CKE). The address port receives address signals and bank address signals. A clock buffer(522) generates internal clock signals(CLK,ZCLK) and outputs it to a control signal buffer(524) and an address buffer(526) and a DLL circuit(400). A row decoder(544) selects a row in a memory cell array(510) according to a row address(XA). A column decoder(546) selects a column in the memory cell array according to a column address(CA). An output circuit(500) comprises a data latch and P/S conversion circuit(536) and an output driver(530).
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申请公布号 |
KR20040042792(A) |
申请公布日期 |
2004.05.20 |
申请号 |
KR20030039680 |
申请日期 |
2003.06.19 |
申请人 |
RENESAS TECHNOLOGY CORP. |
发明人 |
KONO TAKASHI;FURUTANI KIYOHIRO |
分类号 |
G11C11/407;G11C7/22;G11C11/40;H03L7/081;(IPC1-7):G11C11/40 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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