发明名称 |
Instruction queue for an instruction pipeline |
摘要 |
An instruction pipeline in a microprocessor, comprising a plurality of pipeline units with each of the pipeline units processing instructions. At least one of the plurality of pipeline units receives the instructions from another of the pipeline units, stores the instructions and reissues at least one of the instructions after a stall occurs in the instruction pipeline.
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申请公布号 |
US2004098565(A1) |
申请公布日期 |
2004.05.20 |
申请号 |
US20030601172 |
申请日期 |
2003.06.19 |
申请人 |
ROHLMAN JOSEPH;SABBAVARAPU ANIL;KRICK ROBERT F. |
发明人 |
ROHLMAN JOSEPH;SABBAVARAPU ANIL;KRICK ROBERT F. |
分类号 |
G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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