发明名称 LOOP BACK TEST APPARATUS AND METHOD FOR THE SAME
摘要 PURPOSE: A loop back test apparatus and a method for the same are provided to allow the loop back test apparatus to perform the data serial/parallel conversion of the high speed operation chip and the self test of the data transmission/reception. CONSTITUTION: A loop back test apparatus includes a controller(10), a serial converting block(20), a parallel converting block(30), a first transmission/reception block(40) and a second transmission/reception block(50). The controller(10) controls the loop back test path in response to the test control signal, generates a predetermined low speed parallel loop back test data, compares the low speed parallel data with the predetermined low speed parallel loop back test data and outputs the comparison result as a test result. The serial converting block(20) converts the parallel loop back test data generated at the controller(10) into a high speed serial data. The parallel converting block(30) converts the inputted high speed serial data into a parallel data to supply the parallel data to the controller(10) as the converted low speed parallel data. The first transmission/reception block(40) operates the transmission block to transmit the high speed serial data supplied to the serial converting block(20) in response to the loop back test path or operates the reception block to receive the high speed serial data. And, the second transmission/reception block(50) performs the complementary operation with the first transmission/reception block(40), operates the reception block to transmits the high speed serial data to the first transmission/reception block(40) and operate the transmission block to transmit the high speed serial data to the first transmission/reception block(40).
申请公布号 KR20040041783(A) 申请公布日期 2004.05.20
申请号 KR20020069660 申请日期 2002.11.11
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM, NAM HYEON
分类号 G01R31/28;(IPC1-7):G01R31/28 主分类号 G01R31/28
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