Method and system for a programmable diphase digital phase lock loop

摘要

A method and system is provided for a programmable diphase digital phase lock loop (PDDPLL). The PDDPLL has an input to receive a diphase input signal and an output to provide an output signal that is synchronized to the data edges of the diphase input signal. The system includes a configuration component coupled to the PDDPLL to program selected parameters of the PDDPLL output signal. The PDDPLL may locate two consecutive data edges of the diphase input signal that are a programmed bit time apart to determine the positions of the data edges of a continuous diphase input signal. The PDDPLL may locate a beginning of a packet transmission and cause the programmable diphase digital phase lock loop to output a signal that is synchronized to the data edges of the diphase input signal during the packet transmission and free runs at a programmed rate between packet transmissions.