发明名称 FRAME PULSE GENERATOR
摘要 <P>PROBLEM TO BE SOLVED: To suppress a phase jump caused when two clock generating sections are switched. <P>SOLUTION: The frame pulse generator is provided with: the first clock generating section 10 for generating a frame pulse and a clock on the basis of a first external clock; the second clock generating section 20 for generating a frame pulse and a clock on the basis of a second external clock; and a monitor control section 30 for outputting a signal whereby one of the first and second clock generating sections 10, 20 is selected to be a master and the other of the first and second clock generating sections 10, 20 is selected to be a slave on the basis of the states of the first and second clock generating sections 10, 20, and each of the first and second clock generating sections 10, 20 corrects the phase of the frame pulse generated by its own clock generating section on the basis of the clock generated by the other clock generating section when receiving the signal for designating the slave. <P>COPYRIGHT: (C)2004,JPO
申请公布号 JP2004146984(A) 申请公布日期 2004.05.20
申请号 JP20020307989 申请日期 2002.10.23
申请人 TOSHIBA CORP 发明人 IMADA MIYUKI
分类号 H04J3/06;H04L7/00;H04L7/08 主分类号 H04J3/06
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