| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of regularly performing a high-speed data transfer synchronous to an external clock signal before and after output impedance adjustment in a semiconductor device with a clock generation circuit. <P>SOLUTION: An impedance adjustment circuit 30 generates an internal impedance adjustment signal IMP-UD and an impedance adjustment entry signal IMP-ENT based on an external impedance control signal ext.IMP. A data processing circuit 32 decodes the internal impedance adjustment signal IMP-UD synchronously to an internal clock signal CLK, and generates a 5 bit output buffer drive signal BUFON<4:0>. When the output buffer drive signal BUFON<4:0> is inputted to an output replica circuit 21 in a DLL circuit 20 with an output circuit 10 of the latter stage, the impedance of the output replica circuit is adjusted following the adjustment of output impedance. <P>COPYRIGHT: (C)2004,JPO</p> |
