发明名称 |
Duty cycle correction circuit and delay locked loop having the same |
摘要 |
The present invention provides a duty cycle correction circuit (DCC) and a delay locked loop (DLL) including the same. The inventive duty cycle correction circuit includes: a first clock dividing unit and a second clock dividing unit for dividing an ordinary input clock and a sub ordinary input clock; a first clock mixing unit; a second clock mixing unit; and a logic combination unit for generating a duty cycle correction clock. In addition, the inventive delay locked loop (DLL) includes: a first and second clock dividing unit; a frequency detecting unit; a first variable delaying unit; a second variable delaying unit; a first clock mixing unit; a second clock mixing unit; and a logic combination unit.
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申请公布号 |
US2004095174(A1) |
申请公布日期 |
2004.05.20 |
申请号 |
US20030638994 |
申请日期 |
2003.08.11 |
申请人 |
HONG SANG-HOON;KIM SE-JUN;KOOK JEONG-HOON |
发明人 |
HONG SANG-HOON;KIM SE-JUN;KOOK JEONG-HOON |
分类号 |
H03L7/08;H03K5/156;H03L7/081;H03L7/089;(IPC1-7):H03K3/017 |
主分类号 |
H03L7/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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