DELAY LOCKED LOOP

摘要

PURPOSE: A delay locked loop(DLL) is provided to output the inner clock signal with positioning it at the center of the effective data by automatically controlling the phase of the inner clock signal in the DLL. CONSTITUTION: A delay locked loop(DLL) includes a first DLL, a phase difference detection and counting block(100) and a second DLL. The first DLL generates a first inner clock signal of which phase is synchronized to the external clock signal by using a signal generated by detecting and counting the phase difference of the external clock signal and the first inner clock signal. The phase difference detection and counting block(100) performs the counting by detecting the phase difference between the first inner clock signal and the second inner clock signal. And, the second DLL generates the second inner clock signal with correcting the phase of the first inner clock signal by using a signal which is obtained by adding a signal generated by performing the detection and counting the phase difference between the external clock signal and the first inner clock signal to a signal outputted from the phase difference detection and counting block(100).