| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory which can test easily whether each memory cell is normal or not. SOLUTION: This synchronous type SRAM is provided with a register RG outputting successively data signals D0∼D3 of burst length (four) at the time of a test mode, and a transfer circuit 11 in which the output data signals D0∼D3 of the register RG are given to a memory array 7 and burst write-in is performed, while data signals Q0∼Q4 burst-read-out delaying by one clock cycle from burst write-in are outputted to the outside through an IO buffer 8. Therefore, as a data signal for write-in is not required to give separately and the number of address signals may be less, a test can be simplified. COPYRIGHT: (C)2004,JPO
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