| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory designed for making delay of refresh operation not visible from the outside, reducing a cost and speeding up. SOLUTION: A memory cell is equipped with first and second transistors Tr1 and Tr2 connected in series between a regular access dedicated bit line B (E) and a refresh dedicated bit line B (F), and a capacity element C connected to a connection point of the first and second transistors Tr1 and Tr2. To control terminals of first and second transistors, a regular access dedicated wordline W (E) and a refresh dedicated wordline W (F) are connected, respectively. The semiconductor memory adopts a late write configuration in which writing to a memory cell of a write address inputted from outside is carried out behind by at least one or more prescribed number of write cycles, and has at least a means 130 which determines whether the write address inputted from the outside before prescribed cycles matches with the fresh address. COPYRIGHT: (C)2004,JPO
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