| 摘要 |
PURPOSE: A method for forming interconnection of a semiconductor device is provided to be capable of increasing misalignment margin and reducing the parasitic capacitance between metal lines. CONSTITUTION: A conductive region is formed on a semiconductor substrate(30). An interlayer dielectric(42,46), an etch stop layer(48), and a mold layer(50) are sequentially formed on the resultant structure. A groove is formed by selectively patterning the mold layer and the etch stop layer for exposing the interlayer dielectric. A photoresist pattern is formed on the resultant structure. The photoresist pattern has an opening portion having a larger diameter than the width of the groove on a conductive pad(44). A plurality of contact holes are formed for exposing the conductive region by selectively etching the mold layer and the interlayer dielectric using the photoresist pattern as an etching mask. A plurality of metal lines(64,66,68) are formed in the contact hole and the groove for being electrically connected with the conductive pad.
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