发明名称 |
Processor cache memory as RAM for execution of boot code |
摘要 |
In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.
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申请公布号 |
US2004098575(A1) |
申请公布日期 |
2004.05.20 |
申请号 |
US20020295406 |
申请日期 |
2002.11.15 |
申请人 |
DATTA SHAM M.;ZIMMER VINCENT J.;VAID KUSHAGRA V.;STEVENS WILLIAM A.;SANTONI AMY LYNN |
发明人 |
DATTA SHAM M.;ZIMMER VINCENT J.;VAID KUSHAGRA V.;STEVENS WILLIAM A.;SANTONI AMY LYNN |
分类号 |
G06F9/445;G06F12/08;G06F12/12;(IPC1-7):G06F9/445 |
主分类号 |
G06F9/445 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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