发明名称 Data processor, packet recognition method, and error correction method
摘要 A data processor that increases transmission efficiency. The data processor communicates data to and from a host computer via an interface with a packet including a packet ID. The data processor includes a packet recognition circuit for receiving the packet including the packet ID from the host computer and recognizing the type of the packet from the packet ID. A packet length measuring circuit measures packet length of the packet received from the host computer and determines whether the measured packet length is in accordance with the packet type recognized by the packet determination circuit.
申请公布号 US2004095929(A1) 申请公布日期 2004.05.20
申请号 US20030647446 申请日期 2003.08.26
申请人 FUJITSU LIMITED 发明人 AOSHIMA KAZUHIRO
分类号 H04L1/00;H04L1/18;H04L12/28;H04L29/06;(IPC1-7):H04L12/56;H04J3/24 主分类号 H04L1/00
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