发明名称 METHOD AND DEVICE FOR GENERATING TEST BENCH, AND COMPUTER PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a method and device for generating a test bench, and a computer program, enabling simplifying description for generating the test bench. SOLUTION: A test bench generation easing assembly language (ALET: Assembly Language to Ease Testbench) enabling specifying time for execution of a test instruction for verifying a circuit designed using a hardware description language or a system description language at a relative time from execution of one or a plurality of program instructions to be executed on the circuit for executing simulation of the circuit is developed by describing the test instruction on a program file on which the program instructions are described in an assembly language with being related to the predetermined program instructions. Part of the ALET language is extracted from the program file, and a test bench for executing the test instruction at the predetermined time starting from execution of the related program instructions is automatically generated. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004145670(A) 申请公布日期 2004.05.20
申请号 JP20020310313 申请日期 2002.10.24
申请人 OSAKA INDUSTRIAL PROMOTION ORGANIZATION 发明人 HOSHINO KIYOAKI;KUTSUWA TOSHIRO
分类号 G06F17/50;G01R31/3183;(IPC1-7):G06F17/50 主分类号 G06F17/50
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