发明名称 |
Processor capable of executing packed shift operations |
摘要 |
An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.
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申请公布号 |
US6738793(B2) |
申请公布日期 |
2004.05.18 |
申请号 |
US20010783816 |
申请日期 |
2001.01.14 |
申请人 |
INTEL CORPORATION |
发明人 |
LIN DERRICK CHU;MINOCHA PUNIT;PELEG ALEXANDER D.;YAARI YAAKOV;MITTAL MILLIND;MENNEMEIER LARRY M.;EITAN BENNY;CHENNUPATY SRINIVAS |
分类号 |
G06F7/76;G06F9/30;G06F9/315;(IPC1-7):G06F5/05 |
主分类号 |
G06F7/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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