发明名称 |
Digital system with split transaction memory access |
摘要 |
A digital system having a split transaction memory access. The digital system can access data from a system memory through a read buffer (FIFO) located between the processor of the digital system and the system bus. The read buffer is implemented with two FIFOs, a first incoming data FIFO for reading data, and a second outgoing address FIFO for transmitting read requests. The processor of the digital system can access the data FIFO and read data while the data transfer is still in progress. This decreases the processing latency, which allows the processor to be free to perform additional tasks.
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申请公布号 |
US6738837(B1) |
申请公布日期 |
2004.05.18 |
申请号 |
US20020062111 |
申请日期 |
2002.02.01 |
申请人 |
CRADLE TECHNOLOGIES, INC. |
发明人 |
WYLAND DAVID C. |
分类号 |
G06F13/28;(IPC1-7):G06F13/28 |
主分类号 |
G06F13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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