发明名称 System and method for memory characterization
摘要 A memory characterization system and method using a hierarchically-stitched netlist generation technique. A plurality of leaf cells forming a memory instance are generated based on a minimum area required to encompass an optimal number of memory strap points relating to global signals that span the memory instance. Input and output pins are defined for each tile with respect to the global signals in both horizontal and vertical directions. A parametric dataset is obtained for each tile using an extractor (wherein the memory instance is in post-layout condition) or a pre-layout wire-delay estimator. The parametric netlist for the entire memory instance is assembled by coupling the individual parametric datasets using the input and output pins of the tiles with respect to the global signals.
申请公布号 US6738953(B1) 申请公布日期 2004.05.18
申请号 US20020092056 申请日期 2002.03.05
申请人 VIRAGE LOGIC CORP. 发明人 SABHARWAL DEEPAK;SHUBAT ALEX
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址