Integrable, controllable delay device, delay device in a control loop, and method for delaying a clock signal using a delay device

摘要

A delay device has multiplexers connected in series in a differential configuration. First connections of the multiplexers are connected to the output of an upstream multiplexer. Second inputs of the multiplexers are connected to the input connection to which the signal that is to be delayed can be supplied. A control signal controls the switch position of one of the multiplexers such that its output is connected to the input of the delay device. All the other multiplexers are in the other switch position. This results in the delay device producing a specific delay time. When used in a delay control loop, this results in a jitter-free output signal, even if the operating conditions are fluctuating.